| | |
| | | #include "Log.h" |
| | | |
| | | |
| | | #define ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(name,ws,index,psd) { \ |
| | | #define ADD_EQ_PORT_STATUS_STEP(name,ws,index,psd) { \ |
| | | CEqCassetteTransferStateStep* pStep = new CEqCassetteTransferStateStep(); \ |
| | | pStep->setName(name); \ |
| | | pStep->setWriteSignalDev(ws); \ |
| | |
| | | |
| | | { |
| | | // VCR1 Event Report |
| | | /* |
| | | CEqVcrEventStep* pStep = new CEqVcrEventStep(); |
| | | pStep->setName(STEP_EQ_VCR1_EVENT_REPORT); |
| | | pStep->setWriteSignalDev(0x4a); |
| | | pStep->setReturnDev(0x91e); |
| | | pStep->setVcrEventReportDev(0x5fef); |
| | | if (addStep(STEP_ID_VCR1_EVENT_REPORT, pStep) != 0) { |
| | | delete pStep; |
| | | } |
| | | */ |
| | | |
| | | // VCR Event Report |
| | | // 机器上报扫码结果,扫码器预计安装在巡边检机器上 |
| | | CEqReadStep* pStep = new CEqReadStep(0x5fef, 15 * 2, |
| | | [&](void* pFrom, int code, const char* pszData, size_t size) -> int { |
| | | if (code == ROK && pszData != nullptr && size > 0) { |
| | | decodeVCREventReport((CStep*)pFrom, pszData, size); |
| | | } |
| | | return -1; |
| | | }); |
| | | pStep->setName(STEP_EQ_VCR1_EVENT_REPORT); |
| | | pStep->setProp("Port", (void*)1); |
| | | pStep->setWriteSignalDev(0x4a); |
| | | if (addStep(STEP_ID_VCR1_EVENT_REPORT, pStep) != 0) { |
| | | delete pStep; |
| | | } |
| | |
| | | } |
| | | |
| | | // CEqCassetteTranserStateStep |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P1_CASSETTE_EMPTY, 0xd8, |
| | | STEP_ID_PORT1_CASSETTIE_EMPTY, 0x6050); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P1_CASSETTE_LOAD_EADY, 0xe0, |
| | | STEP_ID_PORT1_CASSETTIE_LOAD_READY, 0x6050); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P1_CASSETTE_LOADED, 0xe8, |
| | | STEP_ID_PORT1_CASSETTIE_LOADED, 0x6050); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P1_CASSETTE_INUSE, 0xf0, |
| | | STEP_ID_PORT1_CASSETTIE_INUSE, 0x6050); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P1_CASSETTE_UNLOAD_EADY, 0xf8, |
| | | STEP_ID_PORT1_CASSETTIE_UNLOAD_READY, 0x60f50); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P1_CASSETTE_BLOCKED, 0x100, |
| | | STEP_ID_PORT1_CASSETTIE_BLOCKED, 0x6050); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P2_CASSETTE_EMPTY, 0xd9, |
| | | STEP_ID_PORT2_CASSETTIE_EMPTY, 0x6070); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P2_CASSETTE_LOAD_EADY, 0xe1, |
| | | STEP_ID_PORT2_CASSETTIE_LOAD_READY, 0x6070); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P2_CASSETTE_LOADED, 0xe9, |
| | | STEP_ID_PORT2_CASSETTIE_LOADED, 0x6070); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P2_CASSETTE_INUSE, 0xf1, |
| | | STEP_ID_PORT2_CASSETTIE_INUSE, 0x6070); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P2_CASSETTE_UNLOAD_EADY, 0xf9, |
| | | STEP_ID_PORT2_CASSETTIE_UNLOAD_READY, 0x6070); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P2_CASSETTE_BLOCKED, 0x101, |
| | | STEP_ID_PORT2_CASSETTIE_BLOCKED, 0x6070); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P3_CASSETTE_EMPTY, 0xda, |
| | | STEP_ID_PORT3_CASSETTIE_EMPTY, 0x6090); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P3_CASSETTE_LOAD_EADY, 0xe2, |
| | | STEP_ID_PORT3_CASSETTIE_LOAD_READY, 0x6090); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P3_CASSETTE_LOADED, 0xea, |
| | | STEP_ID_PORT3_CASSETTIE_INUSE, 0x6090); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P3_CASSETTE_INUSE, 0xf2, |
| | | STEP_ID_PORT3_CASSETTIE_INUSE, 0x6090); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P3_CASSETTE_UNLOAD_EADY, 0xfa, |
| | | STEP_ID_PORT3_CASSETTIE_UNLOAD_READY, 0x6090); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P3_CASSETTE_BLOCKED, 0x102, |
| | | STEP_ID_PORT3_CASSETTIE_BLOCKED, 0x6090); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P4_CASSETTE_EMPTY, 0xdb, |
| | | STEP_ID_PORT4_CASSETTIE_EMPTY, 0x60b0); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P4_CASSETTE_LOAD_EADY, 0xe3, |
| | | STEP_ID_PORT4_CASSETTIE_LOAD_READY, 0x60b0); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P4_CASSETTE_LOADED, 0xeb, |
| | | STEP_ID_PORT4_CASSETTIE_LOADED, 0x60b0); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P4_CASSETTE_INUSE, 0xf3, |
| | | STEP_ID_PORT4_CASSETTIE_INUSE, 0x60b0); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P4_CASSETTE_UNLOAD_EADY, 0xfb, |
| | | STEP_ID_PORT4_CASSETTIE_UNLOAD_READY, 0x60b0); |
| | | ADD_EQ_CASSETTE_TRANSFER_STATE_STEP(STEP_EQ_P4_CASSETTE_BLOCKED, 0x103, |
| | | STEP_ID_PORT4_CASSETTIE_BLOCKED, 0x60b0); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT1_EMPTY, 0xd8, |
| | | STEP_ID_PORT1_EMPTY, 0x6050); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT1_LOAD_EADY, 0xe0, |
| | | STEP_ID_PORT1_LOAD_READY, 0x6050); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT1_LOADED, 0xe8, |
| | | STEP_ID_PORT1_LOADED, 0x6050); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT1_INUSE, 0xf0, |
| | | STEP_ID_PORT1_INUSE, 0x6050); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT1_UNLOAD_EADY, 0xf8, |
| | | STEP_ID_PORT1_UNLOAD_READY, 0x60f50); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT1_BLOCKED, 0x100, |
| | | STEP_ID_PORT1_BLOCKED, 0x6050); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT2_EMPTY, 0xd9, |
| | | STEP_ID_PORT2_EMPTY, 0x6070); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT2_LOAD_EADY, 0xe1, |
| | | STEP_ID_PORT2_LOAD_READY, 0x6070); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT2_LOADED, 0xe9, |
| | | STEP_ID_PORT2_LOADED, 0x6070); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT2_INUSE, 0xf1, |
| | | STEP_ID_PORT2_INUSE, 0x6070); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT2_UNLOAD_EADY, 0xf9, |
| | | STEP_ID_PORT2_UNLOAD_READY, 0x6070); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT2_BLOCKED, 0x101, |
| | | STEP_ID_PORT2_BLOCKED, 0x6070); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT3_EMPTY, 0xda, |
| | | STEP_ID_PORT3_EMPTY, 0x6090); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT3_LOAD_EADY, 0xe2, |
| | | STEP_ID_PORT3_LOAD_READY, 0x6090); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT3_LOADED, 0xea, |
| | | STEP_ID_PORT3_INUSE, 0x6090); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT3_INUSE, 0xf2, |
| | | STEP_ID_PORT3_INUSE, 0x6090); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT3_UNLOAD_EADY, 0xfa, |
| | | STEP_ID_PORT3_UNLOAD_READY, 0x6090); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT3_BLOCKED, 0x102, |
| | | STEP_ID_PORT3_BLOCKED, 0x6090); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT4_EMPTY, 0xdb, |
| | | STEP_ID_PORT4_EMPTY, 0x60b0); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT4_LOAD_EADY, 0xe3, |
| | | STEP_ID_PORT4_LOAD_READY, 0x60b0); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT4_LOADED, 0xeb, |
| | | STEP_ID_PORT4_LOADED, 0x60b0); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT4_INUSE, 0xf3, |
| | | STEP_ID_PORT4_INUSE, 0x60b0); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT4_UNLOAD_EADY, 0xfb, |
| | | STEP_ID_PORT4_UNLOAD_READY, 0x60b0); |
| | | ADD_EQ_PORT_STATUS_STEP(STEP_EQ_PORT4_BLOCKED, 0x103, |
| | | STEP_ID_PORT4_BLOCKED, 0x60b0); |
| | | |
| | | { |
| | | // Received Job Report Upstream#1~9 |
| | |
| | | delete pStep; |
| | | } |
| | | } |
| | | } |
| | | |
| | | int CEFEM::onStepEvent(CStep* pStep, int code) |
| | | { |
| | | int nRet = CEquipment::onStepEvent(pStep, code); |
| | | if (nRet > 0) return nRet; |
| | | |
| | | if (code == STEP_EVENT_READDATA) { |
| | | if (isCassetteTransferStateStep(pStep)) { |
| | | SERVO::CEqCassetteTransferStateStep* pEqCassetteStep = (SERVO::CEqCassetteTransferStateStep*)pStep; |
| | | int id = pEqCassetteStep->getID(); |
| | | if (id == STEP_ID_PORT1_CASSETTIE_EMPTY) { |
| | | |
| | | } |
| | | { |
| | | // Indexer Operation Mode Change |
| | | CEqWriteStep* pStep = new CEqWriteStep(); |
| | | pStep->setName(STEP_EFEM_IN_OP_MODE_CHANGE); |
| | | pStep->setWriteSignalDev(0x070); |
| | | pStep->setDataDev(0x023); |
| | | if (addStep(STEP_ID_IN_OP_CMD_REPLY, pStep) != 0) { |
| | | delete pStep; |
| | | } |
| | | } |
| | | |
| | | |
| | | return 0; |
| | | } |
| | | |
| | | void CEFEM::onTimer(UINT nTimerid) |
| | |
| | | |
| | | return -1; |
| | | } |
| | | |
| | | int CEFEM::getIndexerOperationModeBaseValue() |
| | | { |
| | | return 10000; |
| | | } |
| | | } |