/************************************************************************/
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/*
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*
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* Filename : milfpga.h
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* Revision : 10.41.2936
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* Content : This file contains the defines necessary to use the
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* Matrox Imaging Library FPGA DTK "C" user interface.
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*
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* Comments : Some defines may be here but not yet
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* implemented in the library.
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*
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* Copyright © Matrox Electronic Systems Ltd., 1992-2021.
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* All Rights Reserved
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*************************************************************************/
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#ifndef __MILFPGA_H__
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#define __MILFPGA_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/************************************************************************/
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/* MIL FPGA context identifier type */
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/************************************************************************/
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typedef void* MIL_FPGA_CONTEXT;
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typedef MIL_INT (MFTYPE* MIL_FPGA_HOOK_FUNCTION_PTR)( MIL_INT HookType,
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MIL_ID EventId,
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void* UserDataPtr);
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typedef MIL_INT (MFTYPE* MFPGAINQUIRE)( MIL_ID SystemId,
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MIL_INT FpgaDeviceNum,
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MIL_INT64 InquireType,
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void* ResultPtr);
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/************************************************************************/
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/* MIL FPGA API declaration */
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/************************************************************************/
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MIL_INT MFTYPE MfpgaCommandAlloc( MIL_ID MilSysId,
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MIL_INT DeviceNumber,
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MIL_INT FunctionId,
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MIL_INT SubFunctionId,
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MIL_INT64 FunctionNumber,
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MIL_INT ExecutionMode,
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MIL_INT64 ControlFlag,
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MIL_FPGA_CONTEXT* FpgaCommandContextPtr);
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MIL_INT MFTYPE MfpgaCommandFree( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 ControlFlag);
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#if M_MIL_USE_UNICODE
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MIL_INT MFTYPE MfpgaLoadA( MIL_ID MilSystemId,
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MIL_INT FpgaDeviceNumber,
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MIL_CONST_TEXTA_PTR FirmwareFile,
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MIL_INT64 ControlFlag);
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MIL_INT MFTYPE MfpgaLoadW( MIL_ID MilSystemId,
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MIL_INT FpgaDeviceNumber,
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MIL_CONST_TEXTW_PTR FirmwareFile,
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MIL_INT64 ControlFlag);
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#if M_MIL_UNICODE_API
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#define MfpgaLoad MfpgaLoadW
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#else
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#define MfpgaLoad MfpgaLoadA
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#endif
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#else
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MIL_INT MFTYPE MfpgaLoad( MIL_ID MilSystemId,
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MIL_INT FpgaDeviceNumber,
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MIL_CONST_TEXT_PTR FirmwareFile,
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MIL_INT64 ControlFlag);
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#define MfpgaLoadW MfpgaLoad
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#endif
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void MFTYPE MfpgaSetSource( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_BUFFER_INFO SrcBuf,
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MIL_INT StreamInputNumber,
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MIL_INT64 ControlFlag);
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MIL_INT MFTYPE MfpgaSetDestination(MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_BUFFER_INFO DstBuf,
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MIL_INT StreamOutputNumber,
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MIL_INT64 ControlFlag);
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MIL_INT MFTYPE MfpgaSetLink( MIL_FPGA_CONTEXT SrcFpgaCommandContext,
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MIL_INT SrcStreamPort,
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MIL_FPGA_CONTEXT DstFpgaCommandContext,
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MIL_INT DstStreamPort,
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MIL_INT64 ControlFlag);
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void MFTYPE MfpgaCommandQueue( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 CompletionMode,
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MIL_INT64 QueueType);
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void MFTYPE MfpgaGetRegister( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 RegisterSection,
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MIL_INT Offset,
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MIL_INT Length,
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void *ValuePtr,
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MIL_INT64 ReadAccessFlag);
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void MFTYPE MfpgaSetRegister( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 RegisterSection,
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MIL_INT Offset,
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MIL_INT Length,
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void *ValuePtr,
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MIL_INT64 WriteAccessFlag);
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void MFTYPE MfpgaGetAndSetRegister(MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 SrcRegisterBank,
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MIL_INT SrcOffset,
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MIL_INT64 DstRegisterBank,
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MIL_INT DstOffset,
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MIL_INT64 BitMaskRegisterBank,
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MIL_INT BitMaskOffset,
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MIL_INT Length,
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MIL_INT64 ControlFlag);
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void MFTYPE MfpgaCommandControl( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 ControlType,
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const void *ControlValuePtr);
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void MFTYPE MfpgaCommandInquire( MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 InquireType,
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void *UserVarPtr);
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MIL_INT MFTYPE MfpgaInquire( MIL_ID MilSystemId,
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MIL_INT FpgaDeviceNumber,
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MIL_INT64 InquireType,
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void* UserVarPtr);
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MIL_INT MFTYPE MfpgaControl( MIL_ID MilSystemId,
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MIL_INT FpgaDeviceNumber,
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MIL_INT64 ControlType,
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const void* ControlValuePtr);
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void MFTYPE MfpgaHookFunction( MIL_ID MilSystemId,
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MIL_INT DeviceNumber,
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MIL_INT FunctionId,
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MIL_INT SubFunctionId,
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MIL_INT64 FunctionNumber,
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MIL_INT HookType,
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MIL_FPGA_HOOK_FUNCTION_PTR HookHandlerPtr,
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void *UserDataPtr);
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MIL_INT MFTYPE MfpgaGetHookInfo( MIL_ID EventId,
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MIL_INT64 InfoType,
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void *UserVarPtr);
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/************************************************************************/
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/* Transfer unit Function ID and SubFunction ID definitions */
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/************************************************************************/
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#define FPGA_HOST_2_AVALON_FID 0xC001
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#define FPGA_DMA_READ_2_STREAM_FID 0xC010
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#define FPGA_STREAM_2_DMA_WRITE_FID 0xC011
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#define FPGA_HSSI_2_AVALON_FID 0xC012
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#define FPGA_HLS_FID 0xD000
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#define FPGA_FID 0x1000
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#define IS_HLS_FID(x) ( (x >= FPGA_HLS_FID) && (x < (FPGA_HLS_FID + 0x1000)))
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/************************************************************************/
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/* For Processing unit Function ID definitions */
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/* see milfunctioncode.h */
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/************************************************************************/
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/************************************************************************/
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/* */
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/* MfpgaSetSource, MfpgaSetDestination and MfpgaSetLink */
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/* stream offset defines */
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/* */
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/************************************************************************/
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#define M_FPGA_STREAM_INPUT_BIT 0x10000000
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#define M_FPGA_STREAM_OUTPUT_BIT 0x20000000
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#define M_FPGA_STREAM_IO_MASK (M_FPGA_STREAM_INPUT_BIT | M_FPGA_STREAM_OUTPUT_BIT)
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#define M_FPGA_STREAM_IO_FILTER (~ (M_FPGA_STREAM_INPUT_BIT | M_FPGA_STREAM_OUTPUT_BIT))
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#define M_INPUT0 (M_FPGA_STREAM_INPUT_BIT | 0x00000000)
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#define M_INPUT1 (M_FPGA_STREAM_INPUT_BIT | 0x00000001)
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#define M_INPUT2 (M_FPGA_STREAM_INPUT_BIT | 0x00000002)
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#define M_INPUT3 (M_FPGA_STREAM_INPUT_BIT | 0x00000003)
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#define M_INPUT4 (M_FPGA_STREAM_INPUT_BIT | 0x00000004)
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#define M_INPUT5 (M_FPGA_STREAM_INPUT_BIT | 0x00000005)
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#define M_INPUT6 (M_FPGA_STREAM_INPUT_BIT | 0x00000006)
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#define M_INPUT7 (M_FPGA_STREAM_INPUT_BIT | 0x00000007)
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#define M_INPUT8 (M_FPGA_STREAM_INPUT_BIT | 0x00000008)
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#define M_INPUT9 (M_FPGA_STREAM_INPUT_BIT | 0x00000009)
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#define M_OUTPUT0 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000000)
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#define M_OUTPUT1 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000001)
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#define M_OUTPUT2 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000002)
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#define M_OUTPUT3 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000003)
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#define M_OUTPUT4 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000004)
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#define M_OUTPUT5 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000005)
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#define M_OUTPUT6 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000006)
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#define M_OUTPUT7 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000007)
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#define M_OUTPUT8 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000008)
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#define M_OUTPUT9 (M_FPGA_STREAM_OUTPUT_BIT | 0x00000009)
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/************************************************************************/
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/* */
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/* MfpgaSetSource, MfpgaSetDestination and MfpgaSetLink */
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/* flag defines */
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/* */
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/************************************************************************/
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//#define M_DEFAULT 0x10000000L
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#define M_FPGA_FLAG_TYPE 0xf0000000L
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#define M_FPGA_FLAG_TU_FLAVOR_MASK 0x70000000L
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#define M_FPGA_MULTI_CONTEXT 0x30000000L
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#define M_FPGA_MULTI_STREAM_PORT 0x40000000L
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#define M_FPGA_DONT_INTERSECT 0x80000000L
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#define M_FPGA_TU_NUMBER 0xA0000000L
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#define M_CONTEXT0 (M_FPGA_MULTI_CONTEXT | 0)
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#define M_CONTEXT1 (M_FPGA_MULTI_CONTEXT | 1)
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#define M_CONTEXT2 (M_FPGA_MULTI_CONTEXT | 2)
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#define M_CONTEXT3 (M_FPGA_MULTI_CONTEXT | 3)
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#define M_FPGA_FLIP_VERTICAL 0x01000000L
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#define M_FPGA_FLIP_HORIZONTAL 0x02000000L
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/************************************************************************/
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/* */
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/* MfpgaCommandQueue completion mode defines */
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/* */
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/************************************************************************/
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//#define M_DEFAULT 0x10000000L
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#define M_PROCESSING_COMPLETED 0x00000001L
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#define M_DESTINATION_WRITTEN 0x00000002L
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#define M_SOURCE_READ 0x00000003L
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/************************************************************************/
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/* */
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/* MfpgaCommandQueue flags */
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/* */
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/************************************************************************/
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//#define M_DEFAULT 0x10000000L
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//#define M_WAIT 1L
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#define M_DISPATCH 2L
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#define M_DISPATCH_IMMEDIATE 3L
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/************************************************************************/
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/* */
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/* MfpgaGetRegister/MfpgaSetRegister Register bank defines */
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/* */
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/************************************************************************/
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#define M_USER 0x00000001L
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#define M_STREAMER_BASE 0x00000002L
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#define M_PU_BASE 0x00000003L
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#define M_FPGA_BASE 0x00000004L
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#define M_ABSOLUTE_BASE 0x00000005L
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/************************************************************************/
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/* */
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/* MfpgaGetRegister/MfpgaSetRegister Flag defines */
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/* */
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/************************************************************************/
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#define M_WHEN_DISPATCHED 1
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#define M_WHEN_COMPLETED 2
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#define M_AFTER_DISPATCHED 3
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/************************************************************************/
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/* */
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/* MfpgaGetError */
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/* */
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/************************************************************************/
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#define M_FPGA_ERROR_CODE 1
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#define M_FPGA_ERROR_MESSAGE 2
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#define M_FPGA_ERROR_SYSTEM 3
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#define M_FPGA_ERROR_DELETE 0x80000000L
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/************************************************************************/
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/* */
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/* MfpgaInquire / MfpgaControl */
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/* */
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/************************************************************************/
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#define M_MAX_NB_OF_PUS 512
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#define M_MAX_NB_OF_PORTS 255
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#define M_NUMBER_OF_PU 0x1000
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#define M_NUMBER_OF_TU 0x1001
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#define M_PU_LIST 0x1002
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#define M_TU_LIST 0x1003
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#define M_FPGA_PACKAGE_NAME (0x1005|M_CLIENT_ENCODING)
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#define M_FPGA_PACKAGE_NAME_LENGTH 0x1004
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#define M_FPGA_CONFIGURATION_FILENAME (0x1007|M_CLIENT_ENCODING)
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#define M_FPGA_CONFIGURATION_FILENAME_LENGTH 0x1006
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#define M_FPGA_CONFIG 0x1008
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#define M_FPGA_BUILD_NUMBER 0x1009
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#define M_PU_SELECT 0x1010
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#define M_PU_NAME (0x1100|M_CLIENT_ENCODING)
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/* Reserve next 511 values from (0x1100) */
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/* to (0x12ff) */
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#define M_PU_NAME_LENGTH (M_PU_NAME + M_STRING_SIZE)
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#define M_TU_NAME (0x1300|M_CLIENT_ENCODING)
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/* Reserve next 511 values from (0x1300) */
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/* to (0x14ff) */
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#define M_TU_NAME_LENGTH (M_TU_NAME + M_STRING_SIZE)
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#define M_PU_FID 0x1500
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/* Reserve next 511 values from (0x1500 */
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/* to (0x16ff */
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#define M_TU_FID 0x1700
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/* Reserve next 511 values from (0x1700 */
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/* to (0x18ff */
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#define M_FPGA_CONFIGURATION (0x1900|M_CLIENT_ENCODING)
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/************************************************************************/
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/* */
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/* MfpgaCommandInquire */
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/* */
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/************************************************************************/
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#define M_MINOR_VERSION 0x2000
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#define M_MAJOR_VERSION 0x2001
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#define M_FUNCTION_ID 0x2003
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#define M_INSTANCE_ID 0x2004
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#define M_REG_USER_SIZE 0x2005
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#define M_REG_FULL_SIZE 0x2006
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#define M_REG_USER_OFFSET 0x2007
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#define M_REG_IOCTL_OFFSET 0x2008
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#define M_NUMBER_OF_EVENTS 0x2009
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#define M_CAPABILITY 0x200A
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#define M_SUB_FUNCTION_ID 0x200B
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#define M_NUMBER_OF_INPUTS 2835L // used in milclass.h 0xB13
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#define M_NUMBER_OF_OUTPUTS 2836L // used in milclass.h 0xB14
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// M_PORT_NAME is ored with M_FPGA_STREAM_IO_MASK (0x30000000)
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#define M_PORT_NAME (0x2200|M_CLIENT_ENCODING)
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/* Reserve next 255 values from (0x2200 */
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/* to (0x22FF */
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#define M_PORT_NAME_LENGTH (M_PORT_NAME + M_STRING_SIZE)
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/************************************************************************/
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/* */
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/* MfpgaCommandControl */
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/* */
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/************************************************************************/
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#define M_FPGA_CMD_CTRL_TYPE_MASK 0x0FFFF000L
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#define M_COMPLETION_MODE 0x00003000L
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#define M_STREAM_OUTPUT_FORMAT 0x00004000L
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#define M_FPGA_OVERSCAN 0x00005000L
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#define M_LEFT 0x00000100L
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#define M_RIGHT 0x00000200L
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#define M_TOP 0x00000400L
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#define M_BOTTOM 0x00000800L
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#define M_FPGA_OVERSCAN_POSITION_MASK (M_LEFT|M_RIGHT|M_TOP|M_BOTTOM)
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/************************************************************************/
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/* */
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/* MfpgaHookFunction */
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/* */
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/************************************************************************/
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#define M_END_OF_PROCESSING 0x0001
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#define M_INTERRUPT_OVERRUN 0x0080
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/************************************************************************/
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/* */
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/* MfpgaGetHookInfo */
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/* */
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/************************************************************************/
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//#define M_TIME_STAMP 0x0040
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//#define M_FUNCTION_ID 0x2003
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//#define M_INSTANCE_ID 0x2004
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//#define M_SUB_FUNCTION_ID 0x200B
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#define M_FPGA_DEVICE_NUMBER 0x2100
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#define M_IN_FPGA_INQUIRE_UNKNOWN_SIZE_OF_RANGE(X) (false)
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#define M_IN_FPGA_INQUIRE_STRING_RANGE(X) (((X&~M_CLIENT_TEXT_ENCODING) == M_FPGA_PACKAGE_NAME) || \
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(((X&~M_CLIENT_TEXT_ENCODING) >= M_PU_NAME) && ((X&~M_CLIENT_TEXT_ENCODING) < (M_PU_NAME + M_MAX_NB_OF_PUS))) ||\
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(((X&~M_CLIENT_TEXT_ENCODING) >= M_TU_NAME) && ((X&~M_CLIENT_TEXT_ENCODING) < (M_TU_NAME + M_MAX_NB_OF_PUS))))
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#define M_IN_FPGA_INQUIRE_DOUBLE_RANGE(X) (false)
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#define M_IN_FPGA_INQUIRE_MIL_INT64_RANGE(X) (false)
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#define M_FPGA_INQUIRE_MUST_HAVE_USER_PTR(X) (M_IN_FPGA_INQUIRE_STRING_RANGE(X) || \
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M_IN_FPGA_INQUIRE_UNKNOWN_SIZE_OF_RANGE(X) )
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#ifdef __cplusplus
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}
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#endif
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#if M_MIL_USE_STRING
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#if defined(__cplusplus) && !defined(__MIL_AVX_H__) && (!defined(M_LINUX_KERNEL) || !M_LINUX_KERNEL) && (!defined(M_WINDOWS_NT_KERNEL_MODE) || !M_WINDOWS_NT_KERNEL_MODE)
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inline MIL_INT MFTYPE MfpgaInquire(MIL_ID SystemId, MIL_INT FpgaDeviceNum, MIL_INT64 InquireType, MIL_STRING &ResultPtr)
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{
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MIL_INT RetValue = 0;
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MIL_INT InternalStringSize = 0;
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MfpgaInquire(SystemId, FpgaDeviceNum, InquireType + M_STRING_SIZE, &InternalStringSize);
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if(InternalStringSize > 0)
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{
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ResultPtr.assign(InternalStringSize, MIL_TEXT('\0'));
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RetValue = MfpgaInquire(SystemId, FpgaDeviceNum, InquireType, &ResultPtr[0]);
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ResultPtr.resize(InternalStringSize - 1);
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}
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return RetValue;
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}
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inline void MFTYPE MfpgaCommandInquire(MIL_FPGA_CONTEXT FpgaCommandContext,
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MIL_INT64 InquireType,
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MIL_STRING &UserVarPtr)
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{
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MIL_INT InternalStringSize = 0;
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MfpgaCommandInquire(FpgaCommandContext, InquireType + M_STRING_SIZE, &InternalStringSize);
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if(InternalStringSize > 0)
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{
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UserVarPtr.assign(InternalStringSize, MIL_TEXT('\0'));
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MfpgaCommandInquire(FpgaCommandContext, InquireType, &UserVarPtr[0]);
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UserVarPtr.resize(InternalStringSize - 1);
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}
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return;
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}
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#if M_MIL_USE_VECTOR
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inline MIL_INT MFTYPE MfpgaInquire(MIL_ID SystemId, MIL_INT FpgaDeviceNum, MIL_INT64 InquireType, std::vector<MIL_STRING> &ResultArrayPtr)
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{
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MIL_INT RetValue = 0;
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if(InquireType == M_PU_NAME)
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{
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MIL_INT numberOfPUs = 0;
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MfpgaInquire(SystemId, FpgaDeviceNum, M_NUMBER_OF_PU, &numberOfPUs);
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ResultArrayPtr.resize(numberOfPUs);
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for(MIL_INT i = 0; i < numberOfPUs; i++)
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{
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MIL_INT InternalStringSize = 0;
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MfpgaInquire(SystemId, FpgaDeviceNum, M_PU_NAME + i + M_STRING_SIZE, &InternalStringSize);
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if(InternalStringSize > 0)
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{
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ResultArrayPtr[i].assign(InternalStringSize, MIL_TEXT('\0'));
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RetValue = MfpgaInquire(SystemId, FpgaDeviceNum, M_PU_NAME + i, &ResultArrayPtr[i][0]);
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ResultArrayPtr[i].resize(InternalStringSize - 1);
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}
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}
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}
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else
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{
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if(InquireType == M_TU_NAME)
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{
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MIL_INT numberOfTUs = 0;
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MfpgaInquire(SystemId, FpgaDeviceNum, M_NUMBER_OF_TU, &numberOfTUs);
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ResultArrayPtr.resize(numberOfTUs);
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for(MIL_INT i = 0; i < numberOfTUs; i++)
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{
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MIL_INT InternalStringSize = 0;
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MfpgaInquire(SystemId, FpgaDeviceNum, M_TU_NAME + i + M_STRING_SIZE, &InternalStringSize);
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if(InternalStringSize > 0)
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{
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ResultArrayPtr[i].assign(InternalStringSize, MIL_TEXT('\0'));
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RetValue = MfpgaInquire(SystemId, FpgaDeviceNum, M_TU_NAME + i, &ResultArrayPtr[i][0]);
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ResultArrayPtr[i].resize(InternalStringSize - 1);
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}
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}
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}
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else
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{
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#if M_MIL_USE_SAFE_TYPE
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SafeTypeError(MIL_TEXT("MfpgaInquire"), MIL_TEXT("Inquire type compatible with std::vector<MIL_STRING> overload."));
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#endif
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}
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}
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return RetValue;
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}
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#endif
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#endif
|
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#if M_MIL_USE_VECTOR
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inline MIL_INT MFTYPE MfpgaInquire(MIL_ID SystemId, MIL_INT FpgaDeviceNum, MIL_INT64 InquireType, std::vector<MIL_INT> &ResultArrayPtr)
|
{
|
MIL_INT RetValue = 0;
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MIL_INT numberOfPUs = 0;
|
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if(InquireType == M_PU_LIST)
|
{
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MfpgaInquire(SystemId, FpgaDeviceNum, M_NUMBER_OF_PU, &numberOfPUs);
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if(numberOfPUs)
|
{
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ResultArrayPtr.resize(numberOfPUs);
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RetValue = MfpgaInquire(SystemId, FpgaDeviceNum, InquireType, &ResultArrayPtr[0]);
|
}
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else
|
{
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ResultArrayPtr.resize(0);
|
}
|
}
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else
|
{
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ResultArrayPtr.resize(1);
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RetValue = MfpgaInquire(SystemId, FpgaDeviceNum, InquireType, &ResultArrayPtr[0]);
|
}
|
|
return RetValue;
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}
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#endif
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|
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#endif // __cplusplus
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#endif
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